1. Field of the Invention
The present invention relates to a drive circuit of a plasma display device, and more particularly to a data driver having a function that reduces noise attributed to display data, generated at the time of electrode voltage switching.
2. Related Art
In a plasma display of the surface discharge type, row and column electrodes are provided on two glass substrates, respectively, a dielectric layer being provided above the row electrodes of the row electrode glass substrate and a phosphor layer being provided over the column electrodes of the column electrode glass substrate having partition walls, a discharge space being provided between two substrates facing each other and a gas being sealed between the above-mentioned two substrates, which form display panel having a planar matrix structure, in which the row electrodes and the column electrodes are independently driven, so as to cause a plasma discharge at the intersection (cell) between driven row and column electrodes, thereby exiting the phosphor layer provided on the column electrodes so that it emits light. In the case of a display panel that produces a color display, each column electrode is made up of electrodes for three colors having phosphor layer for red (R), green (G), and blue (B), each of the color electrodes for each column being driven separately so as to produce a color display having a plurality of colors.
Additionally, as the row electrodes, X electrodes and electrodes are provided. The X electrodes provided in common for each row and the Y electrodes provided for each row are alternately disposed. In the above-noted case, when driving these electrodes, a voltage pulse is applied alternating between the X and Y electrodes, thereby causing a discharge that reverses the electrode each half cycle. This type of driving method is known as AC drive method.
In an AC plasma display panel (AC-PDP) as described above, once a discharge occurs between the electrodes of each cell, the electrons and ions generated in the discharge space are accumulated on the phosphor layer, thereby forming a wall charge, after the formation of which it is possible because of the action of the wall charge to cause a discharge with a low voltage, and it is possible to sustain the discharge by alternating this low voltage each half cycle. This function is called as a memory function, the discharge sustained by the low voltage based on the memory function is called as sustaining charge.
In an AC-PDP, in order to achieve a gradation representation, the video signal during a single field period is divided into a plurality of sub-fields, the time (number of times) during which a discharge is sustained for each sub-field being controlled. More specifically, for each sub-field, after resetting, by assigning a sustaining discharge period that increases in proportion to 2n, for example, the greater is the number of sustaining discharges made, the brighter will be the light from a cell, thereby performing a gradation representation.
The configurations of an AC-PDP and a conventional data driver circuit and the operation thereof are described below.
FIG. 9 of the accompanying drawings, is a block diagram showing the configuration of an AC color PDP to which the prior art and the present invention could be applied, FIG. 10 is a drawing showing the configuration of a data driver circuit of the past, FIG. 11 is a timing diagram showing the format of the display data input to the data driver circuit, and FIG. 12 is a flowchart illustrating the output operation of the data driver circuit.
As shown in FIG. 9, an AC-PDP 100 has a plurality of data driver circuits 101A, 101B, 101C, . . . , 101E, an AC type plasma display panel (AC-PDP) 102, scan driver circuits 103A, . . . , 103C, a format conversion circuit 104, a drive signal generating circuit 105, and a high-voltage drive circuit 106.
The data driver circuits 101A, 101B, 101C, . . . , 101E, which are formed by integrated circuits, receive from the format conversion circuit 104 a prescribed number (n) of serial display data signals at a time corresponding to the N column electrodes, and output data in parallel to the column electrodes for each scan period in response to a parallel latch control signal from the drive signal generating circuit 105.
The AC-PDP 102 is an AC-driven type plasma display panel, which performs drive in accordance with a sub-field sequence using a memory function, and has a matrix electrode arrangement having M rows of row electrodes and N columns of column electrodes (data electrodes) corresponding to the three colors R, G, and B for each of the columns. The scan driver circuits 103A, . . . , 103C, which are formed by integrated circuits, in response to row drive signals from the drive signal generating circuit 105 for each prescribed number of rows, sequentially output scan signals to the M rows of row electrodes.
The format conversion circuit 104 converts the format of video data having the three colors R, B, and G by using frame memories 111, and the converted three colors R, G, and B signals are sequentially arranged for each column, and the serial display data signals are output from the format conversion circuit 104.
The drive signal generating circuit 105, in response to a vertical synchronization signal included in the video data signal detected by a vertical synchronization signal detection circuit (not shown in the drawing), according to a prescribed sequence for each field, generates row and column drive signals, and supplies these signals to the data driver circuits 101A, 101B, 101C, . . . , 103E, and to the scan driver circuits 103A, . . . , 103C. The high-voltage drive circuit 106, in response to a drive signal from the drive signal generating circuit 105, supplies a high-voltage to each of the data driver circuits 101A, 101B, 101C, . . . , 101E.
A data driver circuit 101 of the past, as shown in FIG. 10, generally comprises an n-stage shift register circuit 11, a parallel latch circuit 12 with n circuits, n output control logic gates G1, G2, G3, G4, . . . , Gn, and n high withstand voltage CMOS (complementary metal oxide semiconductor) drivers B1, B2, B3, B4, . . . , Bn. In the AC-PDP 102 as shown in FIG. 10, the electrode structure for each of the three colors R, G, and B in each column is abbreviated to just a single data electrode DL that is shown.
The shift register circuit 11 is formed by an n-stage shift register, and acts to shift the serial display data signal DS input from the frame memory 111 for each scan period at a time. The parallel latch circuit 12 latches the outputs from the n-stage shift register of the shift register circuit 11 in response to a parallel latch control signal "PHgr" from the drive signal generating circuit 105.
The output control gate circuits G1, G2, G3, G4, . . . , Gn, in response to an output control signal OS from the drive signal generating circuit 105, output signals Q1, Q2, Q3, Q4, . . . , Qn from the parallel latch circuit 12 for each scan period. The high-voltage CMOS drivers B1, B2, B3, B4, . . . , Bn, by using the high-voltage supply Vd from the high-voltage drive circuit 106, convert the parallel signals Q1, Q2, Q3, Q4, . . . , Qn from the output control gate circuits G1, G2, G3, G4, . . . , Gn to data signals O1, O2, O3, O4, . . . , On, which are high-voltage write pulses, these being output to the data electrodes of the AC-PDP 102.
The output states of the data driver circuit 111, as shown in FIG. 11, have two forms. In FIG. 11, FIG. 11(a) shows the case of 1-bit data output, and FIG. 11(b) shows the case of 3-bit data output.
In the case of 1-bit data output, as shown in FIG. 11(a), the input data DS are repeatedly arranged in the sequence of R, G, and B, the shift register circuit 11 shifts these data DS at each rising edge of the shift clock, and when the final shift is reached, at the falling edge, for example, of the parallel latch control signal the data are latched into the parallel latch circuit 12, output being made therefrom one bit at a time, for example as the serial display data signal sequence On, On-1, On-2, On-3, On-4, On-5, On-6, . . . , O3, O2, O1.
In the case of 3-bit data output, as shown in FIG. 11(b), although input data DS are same data as FIG. 11(a), R, G, and B input data are grouped by 3 bits at a time in the sequence of R, G, and B, then the shift register circuit 11 shifts R, G, and B at a rising edge of the shift clock signal SC. When the shift register circuit 11 shifts the last input data, the shifted data by the shift register circuit 11 is latched by the parallel latch circuit 12 at the falling edge of the parallel latch control signal "PHgr". The serial display data signal 1, the serial display data signal 2, and the serial display data 3 are grouped into one group, and output by 3 bits at a time in the sequence (On, On-1, On-2), (On-3, On-4, On-5), (On-6, On-7, On-8) . . . , (O3, O2, O1).
The operation of an AC-PDP device of the past is described below, with references to FIG. 9 through FIG. 12.
An AC-PDP has a configuration such as shown in FIG. 9, in which a video data signal serially input to the format conversion circuit 104 for each of the colors R, G, and B is divided in accordance with number of data outputs from the data driver circuit 101, and converted data are transferred serially to each data driver circuit 101A, 101B, 101C, . . . , 101E during the scan period by using separate signal lines.
At each of the data driver circuits, the serial display data signal DS for each color that was transferred in serial fashion, in response to the shift clock signal SC, is arranged in an R, G, and B sequence and input to the shift register circuit 11, the output from the shift register circuit 11 being latched by the parallel latch circuit 12 in accordance with the parallel latch control signal "PHgr". Parallel output signals are generated in the output control logic gate circuits G1, G2, G3, G4, . . . , Gn, in response to the output control signal OS. These parallel output signals are input to the high-voltage CMOS driver B1, B2, B3, 4, . . . , Bn at the same time so as to generate the high-voltage write pulse data signals O1, O2, O3, O4, . . . , On, then these high-voltage write pulse data signals are output to each of the data electrodes of the AC-PDP 102.
In this case, at each of the data driver circuits, as shown in FIG. 12, in response to the rising edge of the output control signal OS, by inputting the parallel input signal Q to the high-voltage CMOS driver B via the output control logic gate circuit G, conversion is made of the high level of the parallel input signal Q to the high power supply voltage Vd, and conversion is made of the low level to 0 V for output, so that, in response to the parallel input signal Q, the high power supply voltage Vd is applied to the data electrode, thereby causing a discharge at a cell at an intersection with a row electrode that is being scanned.
In a AC-PDP of the past, when data is written to the data electrodes during sub-fields from the data driver circuit, between a given sub-field and a sub-field therebefore or thereafter if the data changes from the condition in which all the data signals are xe2x80x9conxe2x80x9d state to the condition in which all the data signals are xe2x80x9coffxe2x80x9d state, or if the levels of all the data signals change in the reverse direction from the above, there is the problem of noise occurring at the data electrodes of the AC-PDP when switching occurs of the high-voltage of the data signals.
FIG. 13 is a timing diagram illustrating the noise occurring in a data driver circuit of the past and FIG. 14 is a timing diagram illustrating noise occurring in a data driver circuit of the past.
FIG. 13 shows the case in which adjacent outputs are switched to be the same potential, in which case when the parallel input signals Q1, Q2, and Q3 corresponding to the three adjacent data electrodes drive the high-voltage CMOS drivers G1, G2, and G3, so as to drive the high-voltage CMOS drivers B1, B2, and B3, the high power supply voltage Vd being switched so as to convert it to the data signals O1, O2, and O, the voltages at each of the data electrode are relatively the same, and because it is not possible to achieve a discharge load by means of the inter-electrode capacitances C1 and C2 between adjacent electrodes, a sudden change in voltage occurs, thereby causing the large switching noise indicated by the arrows at the rising edge and falling edge of each of the data signals.
In FIG. 14, which shows the case in which there is switching of adjacent outputs that are mutually differing potential at the same time, similar to the case shown in FIG. 13, the parallel input signals Q1, Q2, and Q3 corresponding to three adjacent data electrodes cause switching of the high-voltage supply voltage Vd at the respective high withstand voltage CMOS drivers B1, B2, and B3, so as to convert it to the data signals O1, O2, and O, the voltages at each of the data electrodes being relatively increased, resulting in switching noise at the rising edge and falling edge of each data signal being suppressed. In this case, because it is possible to achieve a discharge load by means of the inter-electrode capacitances C1 and C2 between adjacent electrodes.
In an AC-PDP, depending upon the spatial and temporal arrangement of the display data, there are cases in which the changes that will be a same potential at the same time on adjacent data electrodes occur, in which case, as shown in FIG. 13, charging and discharging of the electrostatic charge between the electrodes do not occur, so that there is a sudden rise in the voltage waveform and the switching currents of the adjacent data electrodes flow in the same direction, resulting in a large amount of noise occurring.
This noise causes a change in the ground level, and this noise becomes an interference noise to the display data. Such interference can manifest itself as dot or line noise on the display screen that is not existent in the original video signal, or noise propagating on the power line increases, or an EMI (electromagnetic interference) increases.
Accordingly, the present invention was made in consideration of the above-noted situation, and has as an object to provide a data driver circuit which, in an AC-PDP or the like, by reducing the opportunity for a change that becomes the same potential at the same time on adjacent data electrodes to occur, achieves a charging/discharging load between adjacent data electrodes at the time of switching of high-voltage data on a data electrode based on a change in the display data, thereby suppressing a sudden change in the switching voltage waveform and reducing the occurrence of noise.
To achieve the above-noted object, the present invention has the following basic technical constitution.
The first aspect of the present invention is a data driver circuit for a plasma display device having a first data electrode and a second electrode that are disposed adjacently to each other, the data driver circuit comprising: a first circuit means for outputting first display data to the first data electrode; a second circuit means for outputting second display data to the second data electrode; and an output timing control means for controlling a timing of outputting the first display data from the first circuit means to the first data electrode or a timing of outputting the second display data from the second circuit means to the second data electrode.
The second aspect of the present invention is a data driver circuit for a plasma display device having a first data electrode and a second electrode that are disposed adjacently to each other, the data driver circuit comprising: a first latch circuit for latching first display data for outputting to the first data electrode; a second latch circuit for latching second display data for outputting to the second data electrode; a first latch signal for the first latch circuit; a second latch signal for the second latch circuit; and a latch timing control means for controlling a latch timing of the first display data by the first latch signal or a latch timing of the second display data by the second latch signal; wherein the latch timing of the second latch circuit is different from that of the first latch circuit.
In the third aspect of the present invention, the data driver circuit further comprising: a time difference generating means for controlling the latch timing control means in accordance with the first display data and the second display data; wherein the time difference generating means generates a time difference between the latch timing of the first latch circuit and the latch timing of the second latch circuit.
The fourth aspect of the present invention is a data driver circuit for a plasma display device having a first data electrode and a second electrode that are disposed adjacently to each other, the data driver circuit comprising: a first circuit means for outputting first display data to the first data electrode at a first timing; a second circuit means for outputting second display data to the second data electrode at the first timing or a second timing that is different from the first timing; and an output timing control means for selecting either the first timing or the second timing so as to control an output timing of the second circuit means.
The fifth aspect of the present invention is a data driver circuit for a plasma display device having a first data electrode and a second electrode that are disposed adjacently to each other, the data driver circuit comprising: a first latch circuit for latching first display data for outputting to the first data electrode; a second latch circuit for latching second display data for outputting to the second data electrode; a latch signal for the second latch circuit; and a latch timing control means for controlling a latch timing of the second display data by the latch signal; wherein the latch timing of the second latch circuit is different from that of the first latch circuit.
The sixth aspect of the present invention is a data driver circuit for a plasma display device having a first data electrode and a second electrode that are disposed adjacently to each other, the data driver circuit comprising: a first latch circuit for latching first display data for outputting to the first data electrode; a second latch circuit for latching second display data for outputting to the second data electrode; a first latch signal for the first latch circuit; and a second latch signal, a latch timing of which being different from that of the first latch circuit, for the second latch circuit.
The seventh aspect of the present invention is a data driver circuit for a plasma display device having a first data electrode and a second electrode that are disposed adjacently to each other, the data driver circuit comprising: a first circuit means for outputting first display data to the first data electrode; a second circuit means for outputting second display data to the second data electrode; and a delay means provided in the second circuit means so as to delay an output timing of the second display data with respect to that of the first display data.